CE Amplifier Calculator

Design a common-emitter amplifier with voltage divider biasing. This topology trades some gain for stable, predictable operation across transistor variations.

Schematic

Calculated Values

Component values rounded to standard E24 series. The bias resistors (R1, R2) set the DC operating point.

R1 (upper bias):
R2 (lower bias):
Rc (collector):
Re (emitter):
Cin (input):
Cout (output):
Ce (bypass):

Gain Analysis

The gain you actually get depends on source and load impedances. The transistor provides its gain, but some signal is lost at the input (voltage divider with source impedance) and output (voltage divider with load).

Input impedance (Zin):
Output impedance (Zout):
Transistor gain (Av):
Input attenuation:
Output attenuation:
Effective gain:
Expected output:

Input / Output Waveforms

The CE amplifier inverts the signal (180° phase shift) and amplifies it. If the output exceeds the available swing, it clips (flattens) at the peaks.

Load Lines

The DC load line (solid blue) shows the operating path set by Rc + Re. When a load is connected, the AC load line (dashed orange) is steeper because AC sees Rc || Rload. The Q-point (red dot) sits on both lines. The green dashed lines show the maximum swing limits before clipping - left is saturation, right is cutoff. For maximum undistorted output, the Q-point should be centered between these limits.

Frequency Response

Low frequencies are limited by coupling capacitors (Cin, Cout) and bypass capacitor (Ce). High frequencies are limited by the transistor's internal capacitances and β rolloff.

Design Formulas

Click to show step-by-step design procedure

Step 1: Set the DC Operating Point

Choose emitter voltage for thermal stability (typically 10% of Vcc or 1V minimum):

$V_E = \max(0.1 \cdot V_{CC},\; 1\text{V})$
$V_B = V_E + 0.7\text{V}$

Step 2: Calculate Emitter Resistor

$R_E = \frac{V_E}{I_C}$

Step 3: Calculate Intrinsic Emitter Resistance

This is the transistor's internal resistance, temperature dependent ($V_T = kT/q \approx 26\text{mV}$ at 25°C):

$r_e' = \frac{V_T}{I_C} = \frac{26\text{mV}}{I_C}$

Step 4: Calculate Collector Resistor for Desired Gain

Without bypass (stable gain):

$A_v = \frac{R_C}{R_E + r_e'}$ ∴ $R_C = A_v \cdot (R_E + r_e')$

With full bypass (maximum gain):

$A_v = \frac{R_C}{r_e'}$ ∴ $R_C = A_v \cdot r_e'$

Step 5: Verify Operating Point

Check that $V_C$ leaves room for the transistor to operate:

$V_C = V_{CC} - I_C \cdot R_C$
Requirement: $V_C > V_E + 0.3\text{V}$ (active region)

Step 6: Calculate Bias Resistors

Use the "stiff divider" rule - divider current should be ~10× base current:

$I_B = \frac{I_C}{\beta}$
$I_{divider} = 10 \cdot I_B$
$R_{total} = \frac{V_{CC}}{I_{divider}}$
$R_2 = \frac{V_B}{V_{CC}} \cdot R_{total}$
$R_1 = R_{total} - R_2$

Step 7: Calculate Input Impedance

$Z_{in(base)} = \beta \cdot (R_E + r_e')$ [without bypass]
$Z_{in(base)} = \beta \cdot r_e'$ [with bypass]
$Z_{in} = R_1 \parallel R_2 \parallel Z_{in(base)}$

Step 8: Calculate Coupling Capacitors

Size for -3dB at the desired low frequency cutoff:

$C_{in} = \frac{1}{2\pi \cdot f_{low} \cdot Z_{in}}$
$C_{out} = \frac{1}{2\pi \cdot f_{low} \cdot R_{load}}$

Step 9: Calculate Bypass Capacitor (if used)

Must have low impedance at lowest frequency of interest:

$X_{C_E} \ll R_E$ at $f_{low}$
$C_E \approx \frac{10}{2\pi \cdot f_{low} \cdot R_E}$

Step 10: Calculate Effective Gain

Account for loading at input and output:

Input attenuation $= \frac{Z_{in}}{Z_{in} + Z_{source}}$
Output attenuation $= \frac{R_{load}}{R_{load} + R_C}$
Effective gain $= A_v \cdot$ input atten $\cdot$ output atten

Key Relationships

Output impedance: $Z_{out} \approx R_C$
Voltage swing: Limited by $V_C - V_E$ (down) and $V_{CC} - V_C$ (up)
AC load line slope: $-1/(R_C \parallel R_{load})$
DC load line slope: $-1/(R_C + R_E)$

Vcc:	V
Desired gain (Av):	V/V
Input (peak):	mV
Source impedance:	Ω
Low frequency (-3dB):	Hz
Load (optional):	Ω
Bypass Re:
Collector current (Ic):	mA

Transistor:
β (hFE):
fT:	MHz