CE + Emitter Follower Calculator

Design a two-stage amplifier with a Common Emitter (CE) stage directly coupled to an Emitter Follower (EF). The CE provides voltage gain while the EF provides current gain and low output impedance. Direct coupling eliminates an inter-stage capacitor and extends low-frequency response.

Schematic

Calculated Values

Component values rounded to standard E24 series. Q1 uses voltage divider bias, Q2 is biased directly from Q1's collector.

CE Stage (Q1)
R1 (upper bias):
R2 (lower bias):
Rc (collector):
Re1 (emitter):
Ce (bypass):
EF Stage (Q2)
Re2 (emitter):
Coupling Capacitors
Cin (input):
Cout (output):

Operating Points

Q1 (CE Stage)
Vb1:
Ve1:
Vc1:
Ic1:
Vce1:
Q2 (EF Stage)
Vb2 (= Vc1):
Ve2:
Vce2:
Ie2:

Gain Analysis

The CE stage provides voltage gain. The EF stage has near-unity voltage gain but provides current gain and low output impedance for driving loads.

Input impedance (Zin):
Output impedance (Zout):
CE stage gain (Av1):
EF stage gain (Av2):
Input attenuation:
Total gain:
Expected output:
Available swing:

Input / Output Waveforms

The CE stage inverts the signal (180° phase shift). The EF stage does not invert. Net result: output is inverted from input.

Frequency Response

Low frequencies are limited by coupling capacitors. High frequencies are limited by transistor capacitances and β rolloff. Direct coupling eliminates one low-frequency pole.

Design Formulas

Click to show step-by-step design procedure

Direct Coupling Constraint

The key constraint in direct coupling is that Q1's collector voltage sets Q2's base voltage:


                    V_c1 = V_b2

                    V_e2 = V_b2 - 0.7V = V_c1 - 0.7V

Step 1: Set Q2 Operating Point

For maximum swing, set Ve2 around Vcc/3:


                    V_e2 ≈ V_cc / 3

                    R_e2 = V_e2 / I_e2

Step 2: Calculate Q1 Collector Voltage

This is fixed by the direct coupling:


                    V_c1 = V_e2 + 0.7V

Step 3: Set Q1 Emitter Voltage

For Q1 stability, use standard CE biasing:


                    V_e1 = max(0.1 × V_cc, 1V)

                    R_e1 = V_e1 / I_c1

Step 4: Calculate Collector Resistor


                    R_c = (V_cc - V_c1) / I_c1

Step 5: Verify Gain is Achievable

With Rc fixed by biasing, check if desired gain is possible:


                    A_v1 = R_c / (R_e1 + r_e1')   [no bypass]

                    A_v1 = R_c / r_e1'   [with bypass]

Step 6: Calculate Bias Resistors

Standard stiff divider for Q1:


                    V_b1 = V_e1 + 0.7V

                    I_divider = 10 × I_b1

                    R₁ + R₂ = V_cc / I_divider

                    R₂ / (R₁ + R₂) = V_b1 / V_cc

Step 7: Calculate Impedances


                    Input impedance:

                    Z_in(Q1) = β₁ × (r_e1' + R_e1)

                    Z_in = R₁ ∥ R₂ ∥ Z_in(Q1)


                    Output impedance (EF stage):

                    Z_out = (r_e2' + R_c/β₂) ∥ R_e2

Key Advantages of This Topology

Extended low-frequency response: One fewer coupling capacitor
Low output impedance: EF buffer can drive low-impedance loads
High input impedance: CE stage doesn't load the source
Good current gain: β₁ × β₂ overall

Vcc:	V
Desired gain (Av):	V/V
Input (peak):	mV
Source impedance:	Ω
Low frequency (-3dB):	Hz
Load resistance:	Ω
Bypass Re1:
Q1 Collector current (Ic1):	mA
Q2 Emitter current (Ie2):	mA

Transistor:
β (hFE):
fT:	MHz